Date: 10/29/25

Flash and memory prices surge as AI demand shifts global memory production

Memory and flash storage market update

Memory Pricing Update: DRAM and NAND Price Pressure Is Building

Short Answer

Memory buyers should prepare for higher DRAM and NAND pricing, tighter supply, and possible lead-time pressure.

AI and HBM demand are pulling wafer capacity toward high-bandwidth memory, while suppliers are managing DDR4, DDR5, and NAND output more carefully. For upcoming projects, early forecasting and purchase planning can help reduce exposure to price volatility.

Memory pricing is becoming a bigger planning issue for IT, procurement, and infrastructure teams. Analysts report that major memory manufacturers are pushing contract pricing higher as AI demand, HBM production, and tighter supply conditions affect the broader DRAM and NAND market.

For teams planning server upgrades, memory refreshes, storage expansion, AI infrastructure, or lifecycle-extension projects, the practical takeaway is simple: do not wait until a project is ready to deploy before checking supply, pricing, and lead times.

For broader infrastructure planning, visit the Data Center Networking Resource Center. For AI infrastructure planning across memory, networking, optics, and validation, review the AI Networking Infrastructure Guide.

What’s Happening

Several supplier and channel signals point to stronger memory pricing heading into Q4.

Samsung Pricing Pressure

Analysts report Samsung is pushing for DRAM contract price increases of 15 to 30 percent and NAND increases of 5 to 10 percent in Q4.

Micron Quotation Changes

Micron has slowed new quotations in some channels and signaled 20 to 30 percent DRAM price increases.

SK Hynix Expected to Follow

SK Hynix is expected to follow similar pricing actions, adding more pressure to the DRAM channel.

Why Prices Are Climbing

The pricing pressure is tied to AI demand, supplier capacity decisions, and tighter channel availability.

AI and HBM Demand

Chipmakers are shifting more wafer capacity toward High-Bandwidth Memory for AI data centers, which affects the supply balance for other memory categories.

Reduced DDR4 and DDR5 Output

Suppliers are prioritizing higher-margin HBM and maintaining disciplined wafer utilization, which can reduce output across DDR4 and DDR5 channels.

Tighter Supply

With limited availability, suppliers are controlling pricing, lead times, and allocation more aggressively across memory channels.

What to Expect

Infrastructure and procurement teams should plan for higher memory pricing through late 2025, possible lead-time extensions, and continued volatility in DRAM contract pricing across the channel.

Planning takeaway: Memory pricing and availability should be reviewed before finalizing server, storage, AI infrastructure, and lifecycle-extension projects.

Memory pricing market chart

Memory Pricing FAQs

Why are DRAM and NAND prices increasing?

DRAM and NAND pricing pressure is being driven by stronger AI demand, HBM capacity shifts, supplier discipline, and tighter availability across the memory channel.

How does AI demand affect memory pricing?

AI data centers require large amounts of High-Bandwidth Memory. As suppliers allocate more wafer capacity to HBM, availability for DDR4, DDR5, and other memory categories may tighten.

What should procurement teams do during memory price volatility?

Procurement teams should forecast upcoming projects, check current inventory, review lead times, align purchase orders early, and evaluate validated OEM-compatible memory options.

Should teams buy memory earlier during a tightening market?

Teams with confirmed projects should review current pricing and lead times early. Early planning helps reduce exposure to sudden price increases, allocation pressure, and project delays.

How can Axiom help with memory planning?

Axiom can help review memory requirements, current pricing, availability, validated OEM-compatible options, and project timelines so teams can plan purchases before market conditions create deployment risk.

Talk to Axiom

Planning memory purchases for upcoming projects?

Contact Axiom for current pricing, lead times, availability, and validated OEM-compatible memory options before price volatility affects your project timeline.

About the Author

Carlos Berto
VP of Engineering

Dr. Carlos Berto leads Axiom’s Network Engineering team, working directly with enterprise and hyperscale data centers on real-world deployment challenges across optical, memory, and interconnect infrastructure.

With over 25 years in telecommunications and data infrastructure, he has been involved in the design, validation, and troubleshooting of high-speed systems from early 10G networks through today’s 400G, 800G, and emerging 1.6T environments.

His work focuses on where systems fail outside controlled lab conditions signal integrity breakdowns, thermal constraints, and power delivery instability in production environments particularly in AI and HPC deployments.

Dr. Berto holds a Ph.D. in Engineering and contributes technical insights that translate field experience into practical guidance for engineering teams responsible for performance and reliability.

Focus Areas

  • Optical and Interconnect Systems (400G / 800G / 1.6T)
  • AI and HPC Infrastructure
  • Signal Integrity, Thermals, and Power Delivery

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