Date: 12/17/25

Finalizing 400G / 800G / 1.6T BOM: An Optics Selection Guide for System Engineers

 

High Level Pillars

• Why optics decisions become the highest-risk BOM item at 400G / 800G / 1.6T

• Distance-first frameworks for DAC, AEC, AOC, and optical transceivers

• Power, thermals, and port-density tradeoffs at scale

• PAM4 margin realities in real-world AI fabrics

• Interoperability vs compatibility across Cisco, Arista, Juniper/HPE, Dell and NVIDIA environments

• Spares, lifecycle planning, and OEM-alternative validation


As AI clusters move from design to deployment, many engineering teams are entering the final—and most expensive—phase of the build: locking the 400G / 800G / 1.6t bill of materials.

At this stage, GPUs and switches are usually already decided. What remains is often underestimated, yet critical to cluster stability, power efficiency, and future scalability: the optics.

Wrong choices here don’t fail loudly. They surface later as marginal BER at scale, unexpected power draw, thermal constraints in dense fabrics, and costly rework after procurement.

 

 

STEP 1: START WITH DISTANCE (NOT SPEED)

≤ 2 meters → DAC

3–5 meters → AEC (sometimes)

5–30 meters → AOC

30+ meters → Optical transceivers

 

STEP 2: MATCH OPTICS TO PORT DENSITY AND THERMAL BUDGET

At 400G but especially 800G and 1.6T, optics are no longer passive passengers. Module power, faceplate density, and switch port limits must be validated at full density.

 

STEP 3: UNDERSTAND PAM4 MARGINS

PAM4 enables higher speeds with thinner margins. Connector quality, fiber handling, aging optics, and sustained thermals all matter.

 

STEP 4: DECIDE EARLY ON THE INTERCONNECT OPTIONS

AOCs, AECs, and DACs simplify deployment and provide predictable performance. Short-reach optics offer flexibility and sparing advantages. Mixing approaches without policy complicates operations.

 

STEP 5: VALIDATE INTEROPERABILITY, NOT JUST COMPATIBILITY

Compatibility does not guarantee stable operation at scale. Validate optics against real firmware versions, vendors, and sustained load conditions.

 

STEP 6: PLAN FOR SPARES AND LIFECYCLE

Late BOM changes are expensive. Poor spares planning is worse. Align sparing ratios, replacement workflows, and lead-time risk early.

 

HOW WE SEE THIS IN REAL DEPLOYMENTS (AXIOM POV)

In production AI clusters, issues rarely appear at bring-up. They surface months later under sustained load.

Common patterns include marginal BER at scale, thermal-induced instability, firmware-triggered interoperability issues, and spares strategies that slow recovery.

The root cause is rarely vendor quality — it’s assumptions that were never pressure-tested at scale.

 

A PRACTICAL FINAL CHECK

• Are any links operating near published reach limits?

• Are power and thermals validated at full population?

• Is there a clear rationale for each optics choice?

• Can spares be sourced quickly months from now?

 

GLOSSARY

DAC (Direct Attach Copper)
Passive copper cable used for very short distances, typically within a rack.

AEC (Active Electrical Cable)
Copper cable with integrated signal conditioning to extend reach beyond passive DAC limits.

AOC (Active Optical Cable)
Fixed-length cable with integrated optical transceivers, commonly used for short to medium distances.

Optical Transceiver
Removable optical module (QSFP-DD, OSFP, etc.) that uses fiber for longer reach and flexible cabling.

PAM4 (Pulse Amplitude Modulation)
A modulation scheme using four signal levels to achieve higher data rates with reduced voltage margins.

BER (Bit Error Rate)
A measure of signal integrity representing the rate of bit errors in a data stream.

QSFP-DD / OSFP
High-density pluggable form factors commonly used for 400G and 800G optics.

Interoperability
Stable operation across vendors, platforms, firmware versions, and scale conditions.

 

FINAL THOUGHT

At 400G, 800G and 1.6T, optics decisions directly affect performance, cost, and long-term reliability.

A short validation before BOM lock can prevent months of downstream instability, rework and unplanned cost.

About the Author

Carlos Berto
Director of Network Engineering, Axiom

Dr. Carlos Berto, Ph.D., leads Axiom’s Network Engineering division, where he helps enterprise and hyperscale data centers maximize performance, reliability, and energy efficiency.

With more than 25 years of leadership experience in the telecommunications and data infrastructure industries, Dr. Berto has overseen the development of next-generation optical, memory, and interconnect technologies that power modern AI and HPC systems.

A recognized expert in advanced networking, Dr. Berto holds a Ph.D. in Engineering and has authored numerous technical insights on topics ranging from 1.6T transceivers to liquid cooling for AI clusters. His work bridges theory and practice translating complex engineering concepts into actionable strategies that IT leaders can use to future-proof their infrastructure.

Focus Areas

  • Optical and Interconnect Technologies
  • AI and High-Performance Computing (HPC) Infrastructure
  • Network Design and Power Efficiency

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